Switch mode power converters, especially those featuring multi-phase operation require a high frequency on-chip clock source. A relaxation oscillator can be found frequently in switch-mode power converters (SMPC) and biomedical IC (integrated circuit) designs. It is favorable because it can be fully-integrated in a CMOS (complementary metal-oxide semiconductor) process, consumes low power and occupies a small chip area. Therefore, low cost monolithic relaxation oscillator is widely adopted.
A typical relaxation oscillator is constructed by comparators, on-chip resistors and capacitors. Other than process and temperature variations of the RC components, the non-idealities of the comparators limit the accuracy and power optimization of the relaxation oscillator.
FIG. 1A shows a schematic view of an architecture of a typical relaxation oscillator 170. The relaxation oscillator 170 consists of two identical branches A and B 172a, 172b. In each branch 172a, 172b, there are a timing capacitor CT=CTA 173a=CTB 173b, a voltage comparator CMPA 174a, CMPB 174b and charge/discharge MOS (metal-oxide-semiconductor) switches, for example MOS transistors 175a, 176a, 175b, 176b. Using branch A 172a as an example, the transistors 175a, 176a may be electrically coupled to each other, with a source/drain terminal of the transistors 175a, 176a coupled to each other at a node where the timing capacitor CTA 173a and the non-inverting input (+) of the voltage comparator CMPA 174a are also connected to. The gate terminals of the transistors 175a, 176a are electrically coupled to each other to receive a voltage VCLKA. The transistors 175b, 176b, the timing capacitor CTB 173b and the non-inverting input (+) of the voltage comparator CMPB 174b may be similarly connected as described above. The relaxation oscillator 170 also includes a first current source 177 supplying a current IREF1 to the other source/drain terminal of the transistors 175a, 175b. The relaxation oscillator 170 further includes a second current source 178, supplying a current IREF2, connected in series with a resistor RT 179 to provide a reference voltage VREF to the inverting inputs (−) of the voltage comparators CMPA 174a, CMPB 174b. The outputs of the voltage comparators CMPA 174a, CMPB 174b are connected to a latch circuit 180. The latch circuit 180 generates an output VCLKA, which may be provided to the gate terminals of the transistors 175a, 176a and another output VCLKB, which may be provided to the gate terminals of the transistors 175b, 176b. 
FIG. 1B shows an operating timing diagram 190 of the relaxation oscillator 170, illustrating the capacitor voltage and clock output waveforms. Between T0 and T2 (between T2 and T4), VCLKA as represented by waveform 192a (VCLKB as represented by waveform 192b) is low, IREF1 charges CTA 173a (CTB 173b) and therefore VCTA as represented by waveform 193a (VCTB as represented by waveform 193b) ramps up at a rate of IREF1/CT. At T1 (T3), the comparator CMPA 174a (CMPB 174b) detects the crossing of VCTA 193a (VCTB 193b) and VREF as represented by the dotted lines 194 (where VREF=IREF2×RT) and sets VCLKA 192a (VCLKB 192b) to high with a finite delay of TD.
From T2 to T4 (from T4 to T6), VCLKA 192a (VCLKB 192b) is high and therefore VCTA 193a (VCTB 193b) is discharged to 0V. Preferably, the switching period of the oscillator, TSW, depends on only the values of CT and RT. However, the temperature and supply dependent comparator delay TD contribute to frequency variations of the switching frequency.
Relaxation oscillators suffer from problems where the comparator delay extends the switching period which decouples the output clock period of the oscillator from the intended RC time constant. Further, the comparators consume considerable static power such that it can toggle its output with a small delay.
Recently, average voltage feedback (AVF) has been proposed to reduce the frequency variation of a relaxation oscillator. FIG. 2A shows a simplified schematic view of an average voltage feedback (AVF) relaxation oscillator 270 of prior art, while FIG. 2B shows a timing diagram 290 of the AVF relaxation oscillator 270. The AVF relaxation oscillator 270 includes a latch circuit 280 and two identical branches A and B 272a, 272b, including the electrical elements and connections, that are similar to the relaxation oscillator 170 of FIG. 1A, except for the additional resistors 281a, 281b connected to the transistors 275a, 276a, 275b, 276b in each branch A 272a, B 272b. 
The AVF relaxation oscillator 270 includes an active-RC filter, including a resistor RINT 281 and a capacitor CINT 282, with an operation amplifier 283, where RINT and CINT are time-multiplexed to extract the DC (direct current) component or average value of the capacitor voltages VCTA (as represented by waveform 293a), applied via a switch 284a, and VCTB (as represented by waveform 293b), applied via a switch 284b. The capacitor voltages VCTA 293a, VCTB 293b are alternately provided as VINT (as represented by waveform 295) to the resistor RINT 281. The resistor RINT 281 and the capacitor CINT 282 are electrically coupled to an inverting input (−) of the operation amplifier 283. The AVF relaxation oscillator 270 also includes two resistors 285, 286 which act as a potential divider to provide a reference voltage VREF (as represented by the solid lines 294) to a non-inverting input (+) of the operation amplifier 283. The error between the average capacitor voltage and the DC (direct-current) reference voltage VREF is integrated and used to adjust the threshold voltage VC (as represented by the dotted lines 296) to the comparators CMPA 274a, CMPB 274b dynamically. The negative feedback action minimizes the error in steady state and therefore the average capacitor voltage and so the capacitor voltage swing (CVS) are regulated with the presence of a finite comparator delay TD.
FIG. 3 shows a schematic view of a relaxation oscillator 370 with average voltage feedback of the prior art, having a comparator and feedback amplifier design. The relaxation oscillator 370 includes one main comparator 374 arranged in an oscillator core portion 371 of the relaxation oscillator 370 and two auxiliary comparators 374a, 374b arranged in respective control logic portions 372a, 372b of the relaxation oscillator 370. A switched capacitor error integrator 387 is used in this design as part of a switched capacitor (SC) feedback portion 388 of the relaxation oscillator 370 for a smaller chip area. Chopping stabilization is also embedded in the feedback amplifier 389 of the switched capacitor error integrator 387 for lowering the flicker noise contributed by the error integrator for better noise performance. Since the design of the relaxation oscillator 370 uses three comparators 374, 374a, 374b for generating the clocks for switched-capacitor operation, its power consumption is much higher than other designs. However, its noise performance is better than the AVF relaxation oscillator 270 of FIG. 2A.
The comparators in both of the prior art designs illustrated in FIGS. 2A and 3 work like voltage controlled delay cells, which are not power efficient. The static power consumed by the comparators is much higher than the dynamic power required to switch their output from one logic level to the other.